Reiner Pope – Chip design from the bottom up
AI chips are optimized to maximize compute efficiency by minimizing data movement, with systolic arrays enabling massive matrix multiplication efficiency through spatial computation and local storage of weights. The clock cycle synchronizes all chip operations, and design trade-offs center
Sign up to read the full summary
Free AI-powered recaps of every episode, delivered to your inbox.
Free forever for up to 3 podcasts. No credit card required.
Guest
Reiner Pope
interview on Dwarkesh Podcast
Mentions
Books, people, and resources mentioned in this episode.
People
Companies
Products & Tools
Research & Papers
Topics
Listen to This Episode
More from Dwarkesh Podcast
Alex Imas and Phil Trammell – What remains scarce after AGI?
Eric Jang – Building AlphaGo from scratch
David Reich – Why the Bronze Age was an inflection point in human evolution
Reiner Pope – The math behind how LLMs are trained and served
Related episodes
From other shows on similar topics.
Why Cerebras CEO Andrew Feldman Built The World's Largest Computer Chip
Odd Lots
The Reality of AI Economics With Paul Kedrosky
Better Offline
OpenAI CFO Sarah Friar on IPO, AI Rivalries, New Device, and Spending $100B+ on Compute
All-In with Chamath, Jason, Sacks & Friedberg
9 Codex Tips From the Codex Team
The AI Daily Brief: Artificial Intelligence News and Analysis
How to Build the Future: Demis Hassabis
Y Combinator Startup Podcast
How to Actually Implement AI in Your Business Without Wasting Six Months
The Vault Unlocked
Get summaries like this every morning.
Free AI-powered recaps of Dwarkesh Podcast and your other favorite podcasts, delivered to your inbox.
Free forever for up to 3 podcasts. No credit card required.